Some processing systems have processing architectures which are based upon a single central control component which is responsible for all top level processing in the system. An example of this is the DMS (Digital Multiplexed Switch) switch architecture used by Northern Telecom in which the single central control component is a single core processor. When compared with parallel processing architectures, such non-distributed architectures provide the advantage to application programmers of some simplification in terms of resource control, flow control, and allowing memory communication rather than messaging between multiple processors. A potential problem with such an architecture is that serious bottlenecks may develop in the central control component mainly due to the single core processor, particularly as more features are added to applications running on the system.
One of the major problems in a multiprocessor system is in preventing data access collisions due to two or more processors accessing the same data at the same time. A data collision occurs when multiple processors interleave accesses to the same data structure such that an inconsistent state is read or updates are lost. For example, if one program makes multiple reads from a data structure while another program, executing concurrently with the first program, modifies the structure such that some reads are made before the structure is modified, and some after, this would result in an inconsistent state of the data structure being read. Typically in multiprocessor architectures, the software is specifically designed from the start with explicit knowledge of this condition in the system and is therefore designed in such a way as to avoid the problem. Mechanisms for doing this generally provide exclusive access to the memory subject to such collisions via software semaphore techniques, or bus lock techniques. These techniques prevent interleaving accesses to data, and require explicit software knowledge of the nature of collisions and specific mechanisms for avoiding them.
Correct operation of many conventional shared memory multiprocessor architectures requires measures to ensure cache coherency. If one or more processors have a copy of an item from shared memory and one of the processors modifies that item, then the modification must be propagated to the other processors. Cache coherency implementations typically require complex high speed protocols between processors and caches.
In systems where the processing capacity provided by a single processor architecture has been surpassed, a shift towards a parallel processing architecture may provide the required increased processing capacity, but it may not be feasible to rewrite the application code originally written for a single processor so that it will work on a parallel processor architecture, simply because of the immense cost incurred and time required to complete such a task.
In order to achieve the combined goal of using multiple processors with little or no modification to the software which was originally written for a single processor architecture, it is necessary that the protection from data access collisions normally provided by software protection techniques be automatically provided by the system.